A 3D IC connects multiple dies that are vertically stacked on top of each other. Three-dimensional integrated circuits (3D ICs) using through-silicon vias (TSVs) have attracted considerable attention as an important technology these are continuing the decreasing technology process trend that Moore predicted. The CMOS technology process is continuing to decline, and as the design of its integrated circuits becomes more complex, the capability to optimize performance is fast approaching the limit. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. We also insert through-silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three-dimensional integrated circuits. Many methodologies for clock mesh networks have been introduced for two-dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing.
0 Comments
Leave a Reply. |